Bit-Cell Selection Analysis for Embedded SRAM-Based PUF

Abstract

[eng] SRAM devices are becoming one of the most promising alternatives for the implementation of embedded physical unclonable functions as the start-up value of each bit-cell depends largely on the variability related with the manufacturing process. Not all bit-cells experience the same degree of variability, so it is possible that some cells randomly modify their logical starting value, which forces to use some kind of post-processing to assure high reliability in PUF response. Unfortunately, unreliable cells are difficult to be detected in advance. This work proposes a method to estimate the ratio of useful cells in an SRAM implemented with a commercial CMOS technology by characterizing the robustness of the value of the start-up logic state of a cell against external disturbances and the mismatch between the devices of their internal latch.